A description of SDRAMs may be found in the article "Synchronous DRAMs: Designing to the JEDEC Standard" in MICRON Design Line, volume 2, Issue 2, No 2Q93.
Synchronous DRAMs can utilize different CAS latency modes of operation. For example, for a CAS latency of 1, data which is read by its data bus read amplifier arrives at its output buffer after the clock. For a CAS latency of 3, the data waits for the clock at a stage preceding the output buffer. For a latency of 2 there is a race condition between the data and the clock to the output buffer.
In a standard DRAM driven by RAS/CAS signals, it was always certain that its output buffer would be put into a tri-state mode when /CAS was at high logic level. On the falling edge of the /CAS signal, new data would be driven to the output pin for the output tristate driver. If the data had not yet arrived, the output of the tristate driver would remain at an intermediate logic level until data was available.
In SDRAMs operating at high speeds of e.g. 100 MHz or higher, there is no time for the tristate driver to enter the intermediate level between data pulses that it outputs. The output buffer must switch virtually instantaneously between one logical polarity of binary data pulses to the other.